Formal Equivalence Checking and Design Debugging by Shi-Yu Huang , Kwang-Ting (Tim) Cheng
English | PDF | 1998 | 238 Pages | ISBN : 079238184X | 16.7 MB
Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail.